Memory device having adjustable refresh period and method of operating the same

A method of operating a memory having a first row of memory cells and one or more second rows of memory cells, the method comprising:

• obtaining read data from the first row based on an adjustment interval;
• setting a refresh period according to the read data from the first row;
• and
• refreshing, by a hardware circuit, the one or more second rows based on the refresh period.

A memory device, comprising:

• a plurality of rows of memory cells, comprising a first row and one or more second rows;
• a frequency divider configured to generate a refresh clock based on a reference clock and a refresh period;
• a refresh request unit configured to generate a refresh request signal based on the refresh clock;
• and
• an adjustment request unit configured to generate a adjustment request signal based on the reference clock and an adjustment interval;
• a refresh address counter configured to set a row address responsive to the first clock and to be halted responsive to a halt signal;
• a read/write control unit configured to control:
• receiving the adjustment request signal;
• setting the halt signal at a first predetermined logic value responsive to the adjustment signal;
• reading data from the first row;
• and
• refreshing one of the one or more second rows responsive to the refresh request signal if the halt signal is at the first predetermined logic value.