System and Method of High Integrity DMA Operation

A system, comprising:

• at least one processor core;
• at least one memory coupled to the at least one processor core;
• and
• a direct memory access (DMA) unit, comprising:
• a bus interface coupled to the at least one memory;
• a plurality of DMA engines coupled to the bus interface;
• a requestor arbitration unit coupled to the plurality of DMA engines, the requestor arbitration unit configured to receive DMA requestors and assign the received DMA requestors to one or more of the plurality of DMA engines for processing the received DMA requestors;
• a synchronization unit coupled to the requestor arbitration unit, the plurality of DMA engines, and the bus interface;
• and
• a DMA comparator coupled to the synchronization unit and the plurality of DMA engines, wherein the synchronization unit is configured to:
• detect if one of the received DMA requestors is a safety requestor;
• and
• if one of the received DMA requestors is a safety requestor, select at least two DMA engines of the plurality of DMA engines for processing the safety requestor, disable the bus interface coupled to at least one DMA engine of the at least two DMA engines, and enable the DMA comparator to compare the outputs of the at least two DMA engines.

A system, comprising:

• means for receiving DMA requestors;
• means for assigning the received DMA requestors to one or more of a plurality of DMA engines for processing the received DMA requestors, wherein the plurality of DMA engines are coupled to a bus interface, and wherein the bus interface is coupled to one or more memory units;
• and
• if one of the received DMA requestors is a safety requestor:
• means for assigning the safety requestor to at least two DMA engines of the plurality of DMA engines for processing the safety requestor,
• means for disabling the bus interface coupled to at least one DMA engine of the at least two DMA engines, and
• means for comparing the outputs of the at least two DMA engines.