Allocation of alias registers in a pipelined schedule
AssigneeIntel Corporation
InventorsHongbo Rong, Cheng Wang, Hyunchul Park, Youfeng Wu
Life of this patent
Estimating the term…
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AssigneeIntel Corporation
InventorsHongbo Rong, Cheng Wang, Hyunchul Park, Youfeng Wu
Estimating the term…
In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.
A system comprising:
At least one computer readable medium including instructions that when executed enable a system to:
(canceled)
A method comprising:
22-25. (canceled)
Dependencies are inferred from the claim text.