Vectorized lookup of floating point values
AssigneeNuance Communications, Inc.
InventorJustin Vaughn Wick
Life of this patent
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Abstract
Systems and techniques disclosed herein include methods for de-quantization of feature vectors used in automatic speech recognition. A SIMD vector processor is used in one embodiment for efficient vectorized lookup of floating point values in conjunction with fMPE processing for increasing the discriminative power of input signals. These techniques exploit parallelism to effectively reduce the latency of speech recognition in a system operating in a high dimensional feature space. In one embodiment, a bytewise integer lookup operation effectively performs a floating point or a multiple byte lookup.
Claims20
A computer-implemented method comprising:
- loading a first set of data elements into a lookup table having a base address;
- loading a vector register with a translation constant corresponding to an arrangement of the first set of data elements;
- loading a second set of data elements into an index register;
- invoking a vector addition instruction to combine the translation constant and the index register;
- and
- invoking a vector permute instruction on the first set of data elements at the base address and the combined translation constant and index register to decode the second set of data elements into a set of segments in a destination memory.
A system comprising:
- a memory including one or more instructions stored thereon that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
- loading a first set of data elements into a lookup table having a base address;
- loading a first vector register with a translation constant corresponding to an arrangement of the first set of data elements;
- loading a second set of data elements into an index register;
- invoking a vector addition instruction to combine the translation constant and the index register;
- and
- invoking a vector permute instruction on the first set of data elements at the base address and the combined translation constant and index register to decode the second set of data elements into a set of segments in a destination memory.
A computer program product including a non-transitory computer-storage medium having instructions stored thereon for processing data information, such that the instructions, when carried out by a processing device, cause the processing device to perform the operations of:
- loading a first set of data elements into a lookup table having a base address;
- loading a first vector register with a translation constant corresponding to an arrangement of the first set of data elements;
- loading a second set of data elements into an index register;
- invoking a vector addition instruction to combine the translation constant and the index register;
- and
- invoking a vector permute instruction on the first set of data elements at the base address and the combined translation constant and index register to decode the second set of data elements into a set of segments in a destination memory.
Dependencies are inferred from the claim text.