Methods, apparatus, instructions and logic to provide vector sub-byte decompression functionality

A processor comprising:

• a memory to hold one or more instructions specifying a vector sub-byte decompression operation from a source of sub-byte elements to a destination vector of byte elements;
• a decode stage to decode said one or more instructions specifying the vector sub-byte decompression operation;
• one or more execution units, responsive to the one or more decoded instructions, to:
• copy from the source, a first two bytes containing a first sub-byte element of a first bit alignment into a least significant portion of a first vector element, and a second two bytes containing a second sub-byte element of the same first bit alignment into a most significant portion of the first vector element;
• copy from the source, a third two bytes containing a third sub-byte element of a second bit alignment into a least significant portion of a second vector element, and a fourth two bytes containing a fourth sub-byte element of the same second bit alignment into a most significant portion of the second vector element;
• shift the first vector element by a first shift count and the second vector element by a second shift count to align the sub-byte elements to a least significant bit of their respective bytes;
• and
• copy a byte from each of the shifted first and second vector elements' least significant portions into a first destination vector element and from each of the shifted first and second vector elements' most significant portions into a second destination vector element to at least partially restore their original sub-byte order.

A method comprising:

• shuffling a first and a second byte containing a first sub-byte element into a least significant portion of a first vector element, and a third and a fourth byte containing a second sub-byte element into a most significant portion of the first vector element;
• shuffling a fifth and a sixth byte containing a third sub-byte element into a least significant portion of a second vector element, and a seventh and an eighth byte containing a fourth sub-byte element into a most significant portion of the second vector element;
• shifting the first vector element by a first shift count and the second vector element by a second shift count to align the sub-byte elements to a least significant bit of their respective byte;
• and
• shuffling a byte from each of the shifted first and second vector elements' least significant portions into a first destination vector element and from each of the shifted first and second vector elements' most significant portions into a second destination vector element to at least partially restore their original sub-byte order.

A machine-readable medium to record functional descriptive material including one or more executable instructions, which if executed on behalf of a thread of a machine causes the machine to:

• shuffle a first and a second byte containing a first sub-byte element of a first bit alignment into a least significant portion of a first vector element, and a third and a fourth byte containing a second sub-byte element of the same first bit alignment into a most significant portion of the first vector element;
• shuffle a fifth and a sixth byte containing a third sub-byte element of a second bit alignment into a least significant portion of a second vector element, and a seventh and an eighth byte containing a fourth sub-byte element of the same second bit alignment into a most significant portion of the second vector element;
• shift the first vector element by a first shift count and the second vector element by a second shift count;
• and
• shuffle a byte from each of the shifted first and second vector elements' least significant portions into a first destination vector element and from each of the shifted first and second vector elements' most significant portions into a second destination vector element to at least partially restore their original sub-byte order.

A processing system comprising:

• a system memory to hold one or more instructions specifying a vector sub-byte decompression operation from a source of sub-byte elements to a destination vector of byte elements;
• and
• a plurality of processors each processor comprising:
• a decode stage to decode said one or more instructions specifying the vector sub-byte decompression operation;
• one or more execution units, responsive to the one or more decoded instructions, to:
• copy from the source, a first two bytes containing a first sub-byte element of a first bit alignment into a least significant portion of a first vector element, and a second two bytes containing a second sub-byte element of the same first bit alignment into a most significant portion of the first vector element;
• copy from the source, a third two bytes containing a third sub-byte element of a second bit alignment into a least significant portion of a second vector element, and a fourth two bytes containing a fourth sub-byte element of the same second bit alignment into a most significant portion of the second vector element;
• shift the first vector element by a first shift count and the second vector element by a second shift count to align the sub-byte elements to a least significant bit of their respective bytes;
• and
• copy one byte from each of the shifted first and second vector elements' least significant portions into a first destination vector element and from each of the shifted first and second vector elements' most significant portions into a second destination vector element to at least partially restore their original sub-byte order.