Synchronizing a translation lookaside buffer with an extended paging table

A virtualization based system comprising:

• a memory to store an instruction specifying an address space context to identify a portion of an address space for guest addresses of the virtualization based system, the guest addresses to be mapped to host addresses by a page table of the virtualization based system;
• and
• a processor to execute the instruction to cause an invalidation of one or more Translation Lookaside Buffer (TLB) entries with one or more corresponding mappings from the page table for guest addresses of the virtualization based system.