Providing queue barriers when unsupported by an i/o protocol or target device
AssigneeQUALCOMM Incorporated
InventorsAssaf Shacham, Itai Lanel, Maya Haim (Erez)
Life of this patent
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AssigneeQUALCOMM Incorporated
InventorsAssaf Shacham, Itai Lanel, Maya Haim (Erez)
Estimating the term…
A host controller is provided that unilaterally supports queue barrier functionality. The host controller may receive a first task marked with a queue barrier indicator. As a result, the host controller stalls transmission of the first task to a target device. Additionally, the host controller also stalls transmission of any task, occurring after the first task, to the target device. The host controller only sends the first task to the target device once an indication is received from the target device that all previously sent tasks have been processed. The host controller only sends any task, occurring after the first task, to the target device once an indication is received from the target device that the first task has been processed.
A host controller, comprising:
A method operational on a host controller for communicating with a target device, comprising:
A non-transitory processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:
Dependencies are inferred from the claim text.