Forming multiple gate length transistor gates using sidewall spacers
AssigneeApplied Materials, Inc.
InventorsChris Bencher, Adam Brand
Life of this patent
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Abstract
A method of fabricating multiple gate lengths simultaneously on a single chip surface. Hard masking materials which are used as spacers in a field effects transistor generation process are converted into a spacer mask to increase the line density on the chip surface. These hard masking spacers are further patterned by either trimming or by enlarging a portion of a spacer at various locations on a chip surface, to enable formation of multiple gate lengths on a single chip, using a series of process steps which make use of combinations of hydrophobic and hydrophilic materials.
Claims4
A method of increasing the number of features on a semiconductor substrate comprising field effects transistors beyond the number which can be created directly using lithographic imaging tools, wherein said method comprises:
- a) providing a semiconductor substrate surface having an overlying layer of a hydrophobic hard masking material;
- b) depositing a layer of photoresist material over said hydrophobic hard masking material, wherein said photoresist material is generally hydrophilic in nature while capable of attaching to said hydrophobic hard mask material;
- c) patterning said hydrophilic photoresist material to form a photoresist template mask and to expose a portion of said hydrophobic hard mask material layer which is present beneath said template mask on an upper surface of said semiconductor substrate;
- d) depositing a hydrophobic spacer material layer overlying said photoresist template mask and exposed portion of hydrophobic hard mask material;
- e) etching said spacer material layer to form a patterned spacer mask;
- f) etching a pattern of said patterned spacer mask through said hydrophobic hard mask material layer to provide a hard mask;
- and
- g) transferring said pattern from said patterned hydrophobic hard mask to an underlying layer present on an upper surface of said semiconductor substrate.
A method of increasing the number of features on a semiconductor substrate surface comprising field effects transistors beyond the number which can be created directly using lithographic imaging tools, wherein said method comprises:
- a) providing a semiconductor substrate surface having an overlying layer of a hydrophilic hard masking material;
- b) depositing a layer of photoresist material over said hydrophilic hard mask material, wherein said photoresist material is generally hydrophobic in nature, while capable of attaching to said hydrophilic hard masking material;
- c) patterning said photoresist material to form a photoresist template mask and to expose a portion of said hydrophilic hard masking material layer which is present beneath said template mask on an upper surface of said semiconductor substrate;
- d) depositing a hydrophilic spacer material layer overlying said photoresist template mask and exposed portion of hydrophilic hard masking material;
- e) etching said spacer material to form a spacer mask;
- f) etching a pattern of said spacer mask through said hydrophilic hard masking material layer to provide a hard mask;
- and
- g) transferring said pattern from said patterned hydrophilic hard mask to an underlying layer present on an upper surface of said semiconductor substrate.
Dependencies are inferred from the claim text.