US 2015/0029789 A1 · NONVOLATILE MEMORY DEVICE INCLUDING MEMORY CELL ARRAY WITH UPPER AND LOWER WORD LINE GROUPS

Abstract

A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at least one other word line of the multiple word lines is included in a lower word line group. The number of data bits stored in memory cells connected to the at least one word line included in the upper word line group is different from the number of data bits stored in memory cells connected to the at least one other word line included in the lower word line group.

Claims20

Dependent claims

A memory system comprising,

at least one nonvolatile memory device in a plurality of memory blocks, wherein each memory block comprises a plurality of strings in a direction perpendicular to a substrate, wherein each string includes at least one string selection transistor, a plurality of memory cells arranged in a plurality of word lines and a plurality of bit lines and at least one ground selection transistor in series;
and
a memory controller configured to control the at least one nonvolatile memory device for storing n bit data per cell in first memory cells connected to a first word line of the plurality of word lines and n+1 bit data per cell in second memory cells connected to a second word line of the plurality of word lines.

A nonvolatile memory device comprising:

a memory cell array including a plurality of memory blocks, wherein each memory block comprises a plurality of strings in a direction perpendicular to a substrate, wherein each string includes at least one string selection transistor, a plurality of memory cells arranged in a plurality of word lines and a plurality of bit lines and at least one ground selection transistor in series;
an address decoder configured to select a memory block among the plurality of memory blocks corresponding to a row address;
a reading and writing circuit configured to write data received from an external device in a page of the selected memory block in a program operation, and to read data from the page of the selected memory block through the plurality of bit lines in a read operation, wherein the page includes memory cells connected to a selected word line among the plurality of word lines;
and a control logic configured to control the address decoder and the reading and writing circuit in the program operation or the read operation,
wherein the each string is formed by a pillar penetrating insulating materials to contact the substrate,
wherein the pillar is formed of at least one material and includes a channel layer and internal material formed within the channel layer,
wherein at least one word line of the plurality of word lines is included in a first word line group and at least one other word line of the plurality of word lines is included in a second word line group,
wherein n bit data are stored in first memory cells connected to the at least one word line included in the first word line group,
wherein n+1 bit data are stored in second memory cells connected to the at least one other word line included in the second word line group.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/512,965Filed 13 Oct 2014

Priority

KR 10-2011--003796222 Apr 2011

Published

29 Jan 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 16/0408
Using variable threshold transistors, e.g. FAMOS: comprising cells containing floating gate transistors
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series

Nonvolatile memory device including memory cell array with upper and lower word line groups

Life of this patent

Nonvolatile memory device including memory cell array with upper and lower word line groups

Life of this patent

Abstract

Claims20