Methods for operating a finfet sram array
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy Liaw
Life of this patent
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Abstract
A method of operating an SRAM array may include: providing a plurality of bit cells, each of the plurality of bit cells comprising a cross coupled inverter pair; a first pass gate; and a second pass gate. A word line voltage may be applied to the first pass gate and the second pass gate, while a first cell positive voltage supply CVdd may be applied to terminals of the cross coupled inverter pair. The first cell positive voltage supply CVdd may be varied relative to the word line voltage during a selected operation of the plurality of bit cells
Claims20
A method comprising:
- applying a first voltage level to a first array of SRAM cells, the SRAM cells of the first array including only single fin finFET transistors formed on a substrate, and to a second array of SRAM cells, the SRAM cells of the second array including single fin finFET transistors and multiple fin finFET transistors formed on the substrate;
- applying a word line voltage to a word line associated with the first array of SRAM cells;
- and
- lowering the first voltage level applied to the first array of SRAM cells to a level lower than the word line voltage during an operation to write data to the first array of SRAM cells.
A method comprising:
- providing a plurality of bit cells, each of the plurality of bit cells comprising:
- a cross coupled inverter pair comprising a first inverter and a second inverter, each of the first inverter and the second inverter comprising a single fin finFET pull up transistor and a single fin finFET pull down transistor;
- a first pass gate coupled between a bit line and an output of the first inverter, the first pass gate comprising a single fin finFET transistor;
- and
- a second pass gate coupled between a complementary bit line and an output of the second inverter, the second pass gate comprising a single fin finFET transistor;
- applying a word line voltage to the first pass gate and the second pass gate;
- applying a first cell positive voltage supply CVdd to terminals of the pull up transistors of the first inverter and the second inverter;
- and
- varying the first cell positive voltage supply CVdd relative to the word line voltage during a selected operation of the plurality of bit cells.
A method, comprising:
- providing a plurality of bit cells, each of the plurality of bit cells comprising:
- a cross coupled inverter pair comprising a first inverter and a second inverter, each of the first inverter and the second inverter comprising a single fin finFET pull up transistor and a multiple fin finFET pull down transistor;
- a first pass gate coupled between a bit line and an output of the first inverter, the first pass gate comprising a multiple fin finFET transistor;
- and
- a second pass gate coupled between a complementary bit line and an output of the second inverter, the second pass gate comprising a multiple fin finFET transistor;
- applying a word line voltage to the first pass gate and the second pass gate;
- and
- applying a first cell positive voltage supply CVdd to terminals of the pull up transistors of the first inverter and the second inverter during a selected operation of the plurality of bit cells.
Dependencies are inferred from the claim text.