Transistor switch with temperature compensated vgs clamp

A load switch circuit for switching power from a power source to a load, comprising

• an FET load switch configured to control switching power from the power source to the load, the FET load switch including a gate with a gate node, and characterized by a gate-source voltage VGS with a maximum rated value of VGS,MAX;
• switch enable circuitry configured to switch-on the FET switch by supplying a switch-on signal to the FET gate
• gate control circuitry coupled between the FET gate node and the FET source, and configured to control FET VGS during FET switch-on, including charging the FET gate, the gate control circuitry including:
• PTAT ΔVBE current source circuitry including a ΔVBE resistor, and configured to supply to the gate node a PTAT current IPTAT corresponding to a voltage across the ΔVBE resistor;
• VGS clamping circuitry coupled between the gate node and the FET source, and configured to establish a temperature compensated VGS clamping voltage VGS,Clamp at the gate node, the VGS clamping circuitry including
• a PTAT resistor RPTAT, characterized by a temperature coefficient substantially the same as the ΔVBE resistor, coupled to the gate node such that a PTAT voltage [VPTAT=(RPTAT*IPTAT)] is developed across RPTAT;
• at least one CTAT VBE component, characterized by a VBE,CTAT voltage drop with a CTAT temperature coefficient, coupled between RPTAT and the FET source such that a CTAT voltage [VCTAT=VBE,CTAT] is developed across the CTAT VBE component;
• such that (i) the temperature dependence of [VPTAT=(RPTAT*IPTAT)] is compensated by the temperature dependence of [VCTAT=VBE,CTAT], and (ii) the VGS clamping voltage at the gate node corresponds to [VGS,Clamp=VPTAT+VCTAT=(RPTAT*IPTAT)+VBE,CTAT].

A method of controlling FET switch-on with VGS temperature compensation, the FET switch including a gate with a gate node, and characterized by a gate-source voltage VGS with a maximum rated value of VGS,MAX, comprising, during FET switch-on:

• generating a PTAT current IPTAT from a PTAT ΔVBE current source including a ΔVBE resistor, IPTAT corresponding to a voltage across the ΔVBE resistor;
• supplying the IPTAT current to the gate node to control FET switch-on, including charging the FET gate;
• and
• establishing a temperature compensated VGS clamping voltage VGS,Clamp at the gate node with gate control circuitry that includes;
• a PTAT resistor RPTAT, characterized by a temperature coefficient substantially the same as the ΔVBE resistor, coupled to the gate node such that a PTAT voltage [VPTAT=(RPTAT*IPTAT)] is developed across RPTAT;
• at least one CTAT VBE component, characterized by a VBE,CTAT voltage drop with a CTAT temperature coefficient, coupled between RPTAT and the FET source such that a CTAT voltage [VCTAT=VBE,CTAT] is developed across the CTAT VBE component;
• such that (i) the temperature dependence of [VPTAT=(RPTAT*IPTAT)] is compensated by the temperature dependence of [VCTAT=VBE,CTAT], and (ii) the VGS clamping voltage at the gate node corresponds to [VGS,Clamp=VPTAT+VCTAT=(RPTAT*IPTAT)+VBE,CTAT].