Technique for wafer-level processing of qfn packages

A wafer-level package device comprising:

• an integrated circuit chip having a surface;
• at least one pillar extending from the surface, the at least one pillar having an end distal from the surface, the at least one pillar configured to provide an electrical interconnection to the integrated circuit chip;
• a solder layer disposed over the end of the at least one pillar;
• and
• an encapsulation structure disposed over the surface, the encapsulation structure at least partially enclosing the at least one pillar.

A semiconductor device comprising:

• an integrated circuit chip having a surface;
• at least one pillar extending from the surface, the at least one pillar having an end distal from the surface, the at least one pillar configured to provide an electrical interconnection to the integrated circuit chip;
• a solder layer disposed over the end of the at least one pillar;
• an integrated circuit package device disposed over the surface;
• and
• an encapsulation structure disposed over the surface, the encapsulation structure at least partially enclosing the at least one pillar and the integrated circuit package device.