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US 2015/0028422 A1Published application
Analog circuit with improved layout for mismatch optimization
AssigneeMarvell World Trade Ltd.
InventorAlbert Wu
Life of this patent
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Abstract
Embodiments include a semiconductor device comprising: a substrate; a first transistor formed on the substrate; and a second transistor formed on the substrate, wherein a common region of the semiconductor device forms (i) a drain region of the first transistor, and (ii) a source region of the second transistor, and wherein a gate region of the first transistor is electrically coupled to a gate region of the second transistor.
Claims20
A semiconductor device comprising:
- a substrate;
- a first transistor formed on the substrate;
- and
- a second transistor formed on the substrate,
- wherein a common region of the semiconductor device forms (i) a drain region of the first transistor, and (ii) a source region of the second transistor, and
- wherein a gate region of the first transistor is electrically coupled to a gate region of the second transistor.
3 more elements
A method of forming a semiconductor device, the method comprising:
- forming a substrate;
- forming a first transistor on the substrate;
- and
- forming a second transistor on the substrate,
- wherein a common region of the semiconductor device forms (i) a drain region of the first transistor, and (ii) a source region of the second transistor, and
- wherein a gate region of the first transistor is electrically coupled to a gate region of the second transistor.
3 more elements
Dependencies are inferred from the claim text.