Apparatus and method to reduce power delivery noise for partial writes
AssigneeIntel Corporation
InventorsKULJIT S. BAINS, JAMES A. MCCALL, PETE D. VOGT, MICHAEL GUTZMANN
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Abstract
Apparatus, systems, and methods to reduce power delivery noise for partial writes are described. In one embodiment, an apparatus comprises a processor and a memory control logic to insert one or more dummy unit intervals into data in a write operation when a number of state transitions between adjacent unit intervals exceeds a threshold. Other embodiments are also disclosed and claimed.
Claims25
An apparatus comprising:
- a processor;
- and
- a memory control logic to:
- insert one or more dummy unit intervals into data in a write operation when a number of state transitions between adjacent unit intervals exceeds a threshold.
A memory controller comprising logic to:
- insert one or more dummy unit intervals into data in a write operation when a number of state transitions between adjacent unit intervals exceeds a threshold.
A method to manage write operations, comprising:
- inserting one or more dummy unit intervals into data in a write operation when a number of state transitions between adjacent unit intervals exceeds a threshold.
A computer program product comprising logic instructions stored in a non-transitory computer readable medium which, when executed by a controller, configure the controller to perform operations, comprising:
- inserting one or more dummy unit intervals into data in a write operation when a number of state transitions between adjacent unit intervals exceeds a threshold.
Dependencies are inferred from the claim text.