Instruction and logic to provide vector blend and permute functionality

A machine implemented method comprising:

• decoding a first instruction specifying:
• a destination operand of one or more vector registers each comprising a first plurality of data fields to store values of vector elements, a first operand of the one or more vector registers, a size of the vector elements, a second operand of the one or more vector registers, and a third operand;
• and
• responsive to the decoded first instruction:
• reading a plurality of index values from data fields of the size of vector elements in the second operand, each of the plurality of index values having a first selector portion and a second selector portion;
• and
• storing vector element values to a portion of corresponding data fields of the specified size of vector elements in the destination operand, wherein for each of the plurality of data fields, responsive to the respective first selector portion having a first value, a first vector element value is to be copied to a corresponding data field of an intermediate vector result from a corresponding data field of the specified size of vector elements in the first operand, and responsive to the respective first selector portion having a second value, a second vector element value is to be copied to the corresponding data field of the intermediate vector result from a corresponding data field of the specified size of vector elements in the third operand, then responsive to the respective second selector portions, the portion of corresponding data fields of the specified size of vector elements in the destination operand is to be replaced by data fields in the intermediate vector result indexed by the respective second selector portion.

A processing system comprising:

• a memory;
• and
• a first plurality of processors, each of the first plurality of processors comprising:
• one or more vector registers each comprising a first plurality of data fields to store values of vector elements;
• a decode stage to decode a first instruction specifying:
• a destination operand of the one or more vector registers, a first operand of the one or more vector registers, a size of the vector elements, a second operand of the one or more vector registers, and a third operand;
• and
• an execution unit, responsive to the decoded first instruction, to:
• read a plurality of index values from data fields of the size of vector elements in the second operand, each of the plurality of index values having a first selector portion and a second selector portion;
• and
• store vector element values to a portion of corresponding data fields of the specified size of vector elements in the destination operand, wherein for each of the plurality of data fields, responsive to the respective first selector portion having a first value, a first vector element value is to be copied to a corresponding data field of an intermediate vector result from a corresponding data field of the specified size of vector elements in the first operand, and responsive to the respective first selector portion having a second value, a second vector element value is to be copied to the corresponding data field of the intermediate vector result from a corresponding data field of the specified size of vector elements in the third operand, then responsive to the respective second selector portions, the portion of corresponding data fields of the specified size of vector elements in the destination operand is to be replaced by data fields in the intermediate vector result indexed by the respective second selector portion.

An apparatus comprising:

• a decoder to decode an instruction specifying:
• a destination operand of one or more vector registers each comprising a first plurality of data fields to store values of vector elements, a first operand of the one or more vector registers, a size of the vector elements, a second operand of the one or more vector registers, and a third operand;
• and
• execution logic operatively coupled with the decoder and responsive to the decoded instruction, the execution logic comprising:
• register access logic to read a plurality of index values from data fields of the size of vector elements in the second operand, each of the plurality of index values having a first selector portion and a second selector portion;
• blend selection logic to select each of the first plurality of data fields of an intermediate vector result, responsive to the respective first selector portion having a first value, from a corresponding data field in the first operand, and responsive to the respective first selector portion having a second value, from a corresponding data field in the third operand;
• and
• switch logic to replace the portion of corresponding data fields in the destination operand by data fields in the intermediate vector result indexed by the respective second selector portion.