Translating cache hints

A system on chip (SoC) comprising:

• a first bus master, wherein the first bus master communicates on a bus according to a first protocol;
• a memory controller, wherein the memory controller comprises a memory cache, wherein the memory cache is configured to receive cache hints which are compliant with a second protocol, wherein the second protocol is different than the first protocol;
• and
• a first bridge unit, wherein the first bridge unit is configured to translate a first cache hint into a second cache hint, wherein the first cache hint is associated with a first transaction generated by the first bus master, wherein the first cache hint is compliant with the first protocol, wherein the first cache hint is set to a reserved encoding value, and wherein the second cache hint is compliant with the second protocol.