Back to results
US 2014/0369120 A1Published application
Memory Device Including a SRAM Memory Plane and a Non Volatile Memory Plane, and Operating Methods
AssigneeSTMicroelectronics (Rousset) SAS
InventorsFrançois Tailliet, Marc Battista
Life of this patent
Estimating the term…
Abstract
A memory device includes at least one memory cell having a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a supply terminal and secondly to the outputs and to the inputs of the two inverters via a controllable interconnection stage.
Claims26
A memory device comprising:
- an SRAM-type elementary memory cell having first and second inverter coupled to one another crosswise;
- a first non-volatile memory unit having a first non-volatile elementary memory cell with a first floating-gate transistor, the first floating-gate transistor having a first conduction electrode coupled to a supply terminal, a control electrode coupled to a first control line, and a second conduction electrode;
- and
- a second non-volatile memory unit having a second non-volatile elementary memory cell with a second floating-gate transistor, the second floating-gate transistor having a first conduction electrode coupled to the supply terminal, a control electrode coupled to the first control line, and a second conduction electrode;
- a controllable interconnection stage with a first portion coupled between the second conduction electrode of the first floating-gate transistor and an output of the first inverter and a second portion coupled between the second conduction electrode of the second floating-gate transistor and an output of the second inverter;
- and
- a control circuit configured to cause the first and second floating-gate transistors to off when a data item stored in the elementary memory cell is differentially programmed into the first and second non-volatile memory units.
4 more elements
A memory device, comprising:
- a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise;
- and
- two groups, each group having at least two parallel-coupled non-volatile elementary memory cells, the non-volatile elementary memory cells of the two groups being coupled firstly to a supply terminal and secondly to outputs and to inputs of the two inverters via a controllable interconnection stage.
A method of operating a memory device that comprises:
- a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise;
- two groups, each group having a non-volatile elementary memory cell, the non-volatile elementary memory cells of the two groups being coupled firstly to a supply terminal and secondly to outputs and to inputs of the two inverters via a controllable interconnection stage, wherein each non-volatile elementary memory cell includes a floating-gate transistor, all floating-gate transistors having a first conduction electrode coupled to the supply terminal and a control electrode coupled to a first control line;
- wherein the controllable interconnection stage comprises
- a second control line;
- a third control line;
- two first interconnection transistors respectively coupled between second conduction electrodes of the floating-gate transistors of the non-volatile elementary memory cells of the two groups and outputs of the two inverters of the SRAM-type elementary memory cell, and having a control electrode coupled to the second control line;
- and
- two second interconnection transistors respectively coupled between the second conduction electrodes of the floating-gate transistors of the non-volatile elementary memory cells of the two groups and inputs of the two inverters of the SRAM-type elementary memory cell, and having a control electrode coupled to the third control line;
- wherein the method comprises writing a data item stored in the SRAM-type elementary memory cell to the two groups of non-volatile elementary memory cells of the memory cell, the method comprising an erase cycle for the groups of non-volatile elementary memory cells followed by a differential programming cycle;
- and
- wherein the erase cycle comprises:
- turning on the first interconnection transistors by applying a control voltage to the second control line;
- turning off the second interconnection transistors by applying a control voltage to the third control line;
- turning off all floating-gate transistors by applying a programming voltage to the first control line;
- and then
- stopping application of the programming voltage to the first control line so as to put the at least one non-volatile elementary memory cell of one of the groups into a written state and the at least one non-volatile elementary memory cell of the other group into an erased state.
13 more elements
Dependencies are inferred from the claim text.