Method for placing operational cells in a semiconductor device

A method of re-placing a plurality of operational cells of a semiconductor device within a semiconductor physical layout, comprising:

• determining a simulated IR drop value for each of the plurality of operational cells when the semiconductor device will be in use;
• identifying operational cells having a simulated IR drop value above a predetermined threshold;
• determining whether the identified operational cells have a high estimated IR due to simultaneous switching, and if so, the method further comprising:
• determining timing data for each of the plurality of operational cells;
• determining switching activity from RTL or design constraints for each of the plurality of operational cells;
• determining power grid switch locations relative to each of the plurality of operational cells;
• deriving a cost function based upon the determined timing data, switching activity and power grid switch locations;
• and
• re-placing identified operational cells within the semiconductor layout to reduce IR drop;
• wherein the method further comprises:
• determining a simulated IR drop value for each of the plurality of re-placed operational cells when the semiconductor device will be in use;
• and
• determining whether each re-placed operational cell IR drop value is below a predetermined maximum IR drop threshold.