Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process

A method, comprising:

• providing a semiconductor structure, said semiconductor structure comprising a substrate having a frontside and a backside, an electrically conductive feature comprising copper provided at said frontside of said substrate and a low-k interlayer dielectric provided over said electrically conductive feature;
• etching a portion of said interlayer dielectric, a surface of said electrically conductive feature being exposed in the etch process;
• and
• performing a degas process, wherein said semiconductor structure is exposed to a substantially non-ionized gas comprising at least one of hydrogen, nitrogen, a hydrocarbon and ammonia.

A method, comprising:

• providing a semiconductor structure, said semiconductor structure comprising a substrate having a frontside and a backside, an electrically conductive feature comprising copper provided at said frontside of said substrate and an ultra-low-k interlayer dielectric having a dielectric constant of 3 or less provided over said electrically conductive feature;
• etching a portion of said interlayer dielectric, a surface of said electrically conductive feature being exposed in the etch process;
• performing a degas process, wherein said semiconductor structure is exposed to argon, and wherein said semiconductor structure is heated from said backside and from said frontside, wherein said semiconductor structure is heated from an initial temperature to approximately a first process temperature during a first phase of said degas process, and wherein said semiconductor structure is maintained at approximately said first process temperature during a second phase of said degas process, a duration of said first phase of said degas process being shorter than about one-half of a total duration of said degas process, said first process temperature being in a range from about 290-310° C., said total duration of said degas process being in a range from about 50-70 seconds;
• and
• performing a preclean process, said preclean process comprising a first phase wherein said semiconductor structure is exposed to substantially non-ionized hydrogen and a second phase wherein a remote hydrogen plasma is used, a duration of said second phase of said preclean process being in a range from about one-quarter of a total duration of said preclean process to about one-half of said total duration of said preclean process, said total duration of said preclean process being in a range from about 30-50 seconds, wherein said semiconductor structure is heated to a second process temperature in a range from about 300-320° C. during said preclean process.