Methods of fabricating non-planar transistors including current enhancing structures
AssigneeSamsung Electronics Co., Ltd.
InventorsMark S. Rodder, Kang-ill Seo
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Abstract
Methods of fabricating non-planar transistors including current enhancing structures are provided. The methods may include forming first and second fin structures directly adjacent each other overlying a substrate including an isolation layer. The methods may further include forming a spacer on the isolation layer including first and second recesses exposing upper surfaces of the first and second fin structures respectively. The spacer may cover an upper surface of the isolation layer between the first and second recesses. The methods may also include forming first and second current enhancing structures contacting the first and second fin structures, respectively, in the first and second recesses.
Claims21
A method of forming a semiconductor structure in a finFET, the method comprising:
- forming first and second fin structures directly adjacent each other overlying a substrate including an isolation layer, wherein the first and second fin structures contact the isolation layer;
- forming a spacer including first and second recesses exposing upper surfaces of the first and second fin structures respectively on the isolation layer, wherein the spacer covers an upper surface of the isolation layer between the first and second recesses;
- and
- forming first and second current enhancing structures contacting the first and second fin structures, respectively, in the first and second recesses.
-26. (canceled)
Dependencies are inferred from the claim text.