Method of fabricating semiconductor multi-chip stack packages

A method of fabricating a multi-chip stack package, comprising:

• preparing single-bodied lower chips including a wafer-level lower semiconductor chip substrate;
• bonding a package substrate onto a first surface of the single-bodied lower chips;
• filling a lower molding compound between the lower semiconductor chip substrate and the package substrate to form a single-bodied substrate-chip bonding structure;
• separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures;
• preparing wafer level single-bodied upper chips including a wafer-level upper semiconductor chip substrate;
• bonding the plurality of unit substrate-chip bonding structures onto a first surface of the wafer-level upper semiconductor chip substrate;
• filling an upper molding compound between the first surface of the upper semiconductor chip substrate and the unit substrate-chip bonding structure to form a single-bodied semiconductor chip stack structure;
• and
• separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.

A method of manufacturing a semiconductor device, the method comprising:

• forming a set of lower chips in an unseparated configuration;
• attaching a plurality of unit package substrates to the set of lower chips, so that conductive terminals at a surface of each unit package substrate align with conductive terminals at a facing surface of each respective lower chip;
• depositing a molding compound between each unit package substrate and its respective lower chip to form a single-bodied substrate-chip bonding structure;
• and
• performing a separation process on the single-bodied substrate-chip bonding structure to form a plurality of unit substrate-chip bonding structures.