Method, system and computer program for hardware design debugging
OwnerSean Safarpour, Andreas Venerisinventors
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Abstract
A plurality of diagnosis methods are provided for enabling hardware debugging, A first diagnosis method enables hardware debugging by means of time abstraction. A second-diagnosis method enables hardware debugging by means of abstraction and refinement. A third diagnosis method enables hardware debugging by means of QBF-formulation for replicated functions. A fourth diagnosis method enables hardware debugging by means of a max-sat debugging formulation. A system and computer program for implementing the diagnosis methods is also provide.
Claims7
A diagnosis method for the debugging of prefabricated and post-fabricated digital hardware designs comprising the steps of;
- (a) gathering an initial error trace t_e with a predetermined number of clock cycles K_f;
- (b) copying the signal and value pairs from the initial error trace t_e into a new error trace t_e_i for a predetermined number of clock cycles K_f−K_i+l to K_f wherein the length K_i is an initial trace bound and the length t_e_i is K_i<K_f;
- (c) performing debugging using the new error trace t_e_i thereby generating a set of debugging results;
- (d) analyzing the debugging results to determine if the suspect locations returned are the actual errors;
- and
- (e) analyzing the debugging results to determine if they denote one or more error locations.
A diagnosis method for the debugging of prefabricated and post-fabricated hardware designs comprising the steps of:
- (a) converting the hardware design into design conjunctive normal form;
- (b) adding the stimulus and expected response constraints to the design conjunctive normal form;
- (c) generating a map between components in the hardware design and the conjunctive normal form;
- (d) determining a maximal subset of clauses that result in a satisfiable problem;
- (e) inverting the maximal subset of clauses to determine a subset of clauses that result in an unsatisfiable problem;
- and
- (f) using the generated map to relate the inverse set of clauses to the actual components in the hardware design.
Dependencies are inferred from the claim text.