Sense amplifier circuit and semiconductor memory device

A semiconductor memory device, comprising:

• a memory cell array block including n memory cell sub-arrays each memory cell sub-array having bit lines and word lines, where n is an integer greater than 1;
• n+1 sense amplifier arrays located between the n memory cell sub-arrays and at first and second edges of the memory cell array block in a first direction, each sense amplifier array including a plurality of sense amplifier circuits, each sense amplifier circuit comprising:
• a first inverter having an input node coupled to a corresponding first bit line and an output node coupled to a corresponding second bit line;
• a second inverter having an input node coupled to the corresponding second bit line and an output node coupled to the corresponding first bit line;
• and
• a control circuit configured to generate a first sensing signal to activate first inverters of the sense amplifier circuits and a second sensing signal to activate second inverters of the sense amplifier circuits, the first sensing signal being generated prior to activating the second sensing signal.

A method of operating a semiconductor memory device including a plurality of memory cells connected to bit lines and word lines, the method comprising:

• equalizing a first bit line and a second bit line;
• activating a first inverter including an input node coupled to the first bit line and an output node coupled to the second bit line;
• performing a charge sharing between one of the first and second bit lines and a memory cell which is connected to the one of the first and second bit lines and a first word line;
• and
• after a first time period from when the first inverter is activated, activating a second inverter including an input node coupled to the second bit line and an output node coupled to the first bit line,
• wherein the charge sharing occurs by selecting the first word line and
• wherein the first inverter is activated before the selecting the first word line.