Fast, low power comparator with dynamic bias background
AssigneeQUALCOMM Incorporated
InventorVijayakumar Dhanasekaran
Life of this patent
Estimating the term…
Abstract
A comparator circuit comprising an operational amplifier configured to compare a difference between a switching voltage and a reference voltage, and a dynamically adjustable bias current generator coupled to the operational amplifier. A method of conserving power in a comparator circuit includes estimating a switching regulator load current value, communicating the value to a current bias generator, enabling the bias generator with a signal from a switching regulator PFM logic circuit, and establishing a bias current at an operational amplifier of the comparator circuit on the basis of the enabling.
Claims24
A comparator circuit comprising:
- an operational amplifier configured to compare a difference between a switching voltage (Vsw) and a reference voltage (Vref);
- and
- a dynamically-adjustable bias current generator coupled to the operational amplifier, wherein the dynamically-adjustable bias current generator is configured to output a bias current to the operational amplifier.
A method of conserving power in a comparator circuit, comprising:
- estimating a switching regulator load current value;
- communicating the load current value to a current bias generator;
- enabling the bias current generator with an enabling signal from a switching regulator PFM logic circuit;
- and
- establishing a bias current at an operational amplifier of the comparator circuit on the basis of the enabling signal and the estimated load current value.
A non-transitory computer readable media including program instructions which when executed by a processor cause the processor to perform the method of conserving power in a comparator circuit, comprising:
- estimating a switching regulator load current value;
- communicating the load current value to a current bias generator;
- enabling the bias current generator with an enabling signal from a switching regulator PFM logic circuit;
- and
- establishing a bias current at an operational amplifier of the comparator circuit on the basis of the enabling signal and the estimated current value.
A comparator circuit comprising:
- means for comparing a difference between a switching voltage (Vsw) and a reference voltage (Vref);
- and
- means for dynamically adjusting a bias current to the comparing means.
Dependencies are inferred from the claim text.