Methods and systems to stress-program an integrated circuit

A method, comprising:

• asserting complementary logic states at inputs of a first integrated circuit (IC) block to cause the first IC block to assert pre-determined complementary logic states at outputs of the first IC block;
• and
• stressing at least a portion of the first IC block while the complementary logic states are asserted at the inputs, to program the first IC block to assert the pre-determined complementary logic states upon de-activation of a reset control without assertion of the complementary logic states at the inputs.

A non-transitory computer readable medium encoded with a computer program, including instructions to cause a processor to:

• provide complementary logic states to inputs of a first integrated circuit (IC) block to cause the first IC block to assert pre-determined complementary logic states at outputs of the first IC block;
• and
• control a system to stress at least a portion of the first IC block while the complementary logic states are asserted at the inputs, to program the first IC block to assert the pre-determined complementary logic states at the outputs upon de-activation of a reset control without assertion of the complementary logic states at the inputs.

The computer readable medium of claim 23, wherein the first IC block and a second IC block are on a same IC die, and wherein the computer readable medium further includes instructions to cause the processor to:

• configure the first IC block to provide at least one of the pre-determined complementary logic states to the second IC block as a pre-determined compensation value to compensate for one or more of process corner variations and random variations imparted by one or more IC blocks of the IC die.

A system, comprising an integrated circuit (IC) die, including:

• a processor and memory;
• and
• compensation circuitry, including a stress-programmable configuration register to assert a pre-determined configuration register value following a reset to compensate for one or more of process corner variations and random variations imparted by one or more IC blocks of the IC die.