Device

A method to calibrate an impedance of a device having a plurality of stacked semiconductor devices interconnected by through electrodes, the method comprising:

• coupling a resistor between an external terminal of the device and a first voltage source;
• and
• in each semiconductor device of the plurality of stacked semiconductor devices;
• enabling a replica output circuit having a first plurality of PMOS transistors connected between a second voltage source and a first through electrode connected to the external terminal and a first plurality of NMOS transistors connected between a third voltage source and the first through electrode;
• adjusting a PMOS count value to control a number of transistors of the first plurality of PMOS transistors in an on-state until the PMOS count value reaches a final PMOS count value, wherein while the PMOS count value is at the final PMOS count value, a voltage on the external terminal is at a first predetermined voltage;
• storing the final PMOS count value;
• adjusting an NMOS count value to control a number of transistors of the first plurality of NMOS transistors in the on-state until the NMOS count value reaches a final NMOS count value, wherein while the NMOS count value is at the final NMOS count value, the voltage on the external terminal is at a second predetermined voltage;
• storing the final NMOS count value;
• and
• controlling an output circuit having a second plurality of PMOS transistors connected between the second voltage source and a second through electrode and a second plurality of NMOS transistors connected between the third voltage source and the second through electrode using the final PMOS count value and the final NMOS count value, wherein a number of transistors of the second plurality of PMOS transistors in the on-state is determined by the final PMOS count value and the number of transistors of the second plurality of NMOS transistors in the on-state is determined by the final NMOS count value.