Complementary back end of line (beol) capacitor

A method of fabrication a capacitor comprising:

• forming a metal oxide metal (MOM) capacitor structure within lower interconnect layers of an interconnect stack of an integrated circuit (IC) device;
• depositing at least one metal insulator metal (MIM) capacitor layer between a first upper interconnect layer and a second upper interconnect layer of the interconnect stack;
• and
• forming a MIM capacitor structure coupled to the MOM capacitor structure, the MIM capacitor structure comprising a first capacitor plate including at least a portion of the first upper interconnect layer, and a second capacitor plate including at least a portion of the at least one MIM capacitor layer.

A capacitor comprising:

• a means for storing electric charge coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device, the charge storing means including at least one lower interconnect layer of the interconnect stack;
• a second upper interconnect layer of the interconnect stack coupled to the electric charge storing means;
• at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer, and
• a MIM capacitor structure coupled to the electric charge storing means, the MIM capacitor structure comprising a first capacitor plate including at least a portion of the first upper interconnect layer, and a second capacitor plate including at least a portion of the at least one MIM capacitor layer.

A method of fabrication a capacitor comprising:

• steps for forming a metal oxide metal (MOM) capacitor structure within lower interconnect layers of an interconnect stack of an integrated circuit (IC) device;
• steps for depositing at least one metal insulator metal (MIM) capacitor layer between a first upper interconnect layer and a second upper interconnect layer of the interconnect stack;
• and
• steps for forming a MIM capacitor structure coupled to the MOM capacitor structure, the MIM capacitor structure comprising a first capacitor plate including at least a portion of the first upper interconnect layer, and a second capacitor plate including at least a portion of the at least one MIM capacitor layer.