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AssigneesCommissariat A L'energie Atomique Et Aux Energies Alternatives, STMicroelectronics S.r.l.
InventorsBastien Giraud, Jean-Philippe Noel, Maud Vinet
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An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer.
A manufacture comprising an integrated circuit, said integrated circuit comprising a silicon substrate, a ground plane disposed above said silicon substrate, a buried insulator layer disposed above said ground plane, a silicon layer disposed above said buried insulator layer and separated from said ground plane by said buried insulator layer, and an FDSOI transistor having a channel adapted for being formed in said silicon layer, a source and drain disposed in and/or on said silicon layer, and a gate that covers an upper face of said channel and that comprises a lateral portion covering a lateral face of said channel and disposed above said ground plane, a distance between said lateral portion and said ground plane being less than or equal to three nanometers and at least five times less than a thickness of said buried insulator layer between said ground plane and said silicon layer, said ground plane being separated from said gate by said buried insulator layer.
A method of fabricating an integrated circuit, said method comprising providing an element comprising a silicon substrate, a ground plane disposed above said substrate, a buried insulator layer disposed above said ground plane, and a silicon layer disposed above said buried insulator layer and separated from said ground plane by said buried insulator layer, forming a channel of an FDSOI transistor in said silicon layer, forming a source and a drain of said FDSOI transistor in and/or on said silicon layer, and forming a gate of said FDSOI transistor covering an upper face of said channel and comprising a lateral portion covering a lateral face of said channel and disposed above said ground plane, said ground plane being separated from said gate by said buried insulator layer, a distance between said lateral portion and said ground plane being less than or equal to three nanometers and at least five times less than a thickness of said buried insulator layer between said ground plane and said silicon layer.
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