Selectively programming data in multi-level cell memory

An apparatus, comprising:

• flash determination logic, implemented in at least hardware, to identify N access speeds available for accessing a multi-level memory cell device (MLMCD) comprising multi-level cells, wherein the multi-level cells are configured to store at least two bits per cell wherein most significant bits are grouped to define fast access pages and least significant bits are grouped to define slow access pages;
• and
• flash control logic, implemented in at least hardware, to access the MLMCD upon receiving a memory command that is directed to a single type of memory, wherein the MLMCD is to be accessed using one speed of the N access speeds, where the one speed of the N access speeds is selected based on at least one parameter in the memory command;
• wherein the flash control logic is configured to access the MLMCD with the one speed by accessing a group of most significant bits from the MLMCD without accessing a group of least significant bits from the MLMCD;
• and
• wherein, in response to an event, the flash control logic is further configured to program data from a volatile memory to the fast access pages by programming the data into a group of most significant bits while skipping the least significant bits.

An apparatus, comprising:

• a flash memory comprising multi-level cells (MLC), wherein the multi-level cells include most significant bits grouped together to form fast access pages and least significant bits grouped together to form slow access pages, wherein the fast access pages are configured to be programmed faster than the slow access pages;
• program logic implemented in at least hardware configured to program data from a volatile memory to the most significant bits upon detecting that a power quality associated with the volatile memory meets a threshold value;
• wherein program logic is further configured to detect a fast access bit that is part of a bit field in a memory request wherein the fast access bit indicates to program the data from the volatile memory to pages in the flash memory formed by a group of most significant bits;
• and
• wherein the program logic is configured, in response to detecting the fast access bit, to program the data from the volatile memory to pages formed from a group of most significant bits from the multi-level cells while skipping pages formed from the group of least significant bits.