Methods of forming multiple n-type semiconductor devices with different threshold voltages on a semiconductor substrate

A method of forming an integrated circuit product comprised of first and second N-type transistors, wherein said first and second transistors are formed in and above first and second active regions, respectively, comprising:

• performing a common threshold voltage adjusting ion implantation process on said first and second active regions;
• forming said first and second N-type transistors in and above said first and second active regions;
• performing an amorphization ion implantation process to selectively form regions of amorphous material in said first active region but not in said second active region;
• after performing said amorphization ion implantation process, forming a capping material layer above said first and second transistors and above said first and second active regions;
• and
• after forming said capping material layer, performing a re-crystallization anneal process to convert at least portions of said regions of amorphous material to a crystalline material.

A method of forming an integrated circuit product comprised of first and second N-type transistors comprised of first and second replacement gate structures, respectively, wherein said first transistor has a lower threshold voltage than said second transistor and wherein said first and second N-type transistors are formed in and above first and second active regions, respectively, comprising:

• performing a common threshold voltage adjusting ion implantation process on said first and second active regions;
• forming first and second sacrificial gate transistors in and above said first and second active regions, each of said sacrificial gate transistors comprising a sacrificial gate structure;
• performing an amorphization ion implantation process to selectively form regions of amorphous material in said first active region but not in said second active region;
• after performing said amorphization ion implantation process, forming a capping material layer above said first and second sacrificial gate transistors and above said first and second active regions;
• after forming said capping material layer, performing a re-crystallization anneal process to convert at least portions of said regions of amorphous material to a crystalline material;
• performing at least one process operation to remove said sacrificial gate structures of said first and second sacrificial gate transistors to thereby define first and second gate cavities, respectively;
• and
• forming said first and second replacement gate structures in said first and second gate cavities, respectively.