Method for producing semiconductor device and semiconductor device

A method for producing a semiconductor device, the method comprising:

• a first step comprising:
• forming a first fin-shaped silicon layer and a second fin-shaped silicon layer on a substrate that are connected to each other at their ends to form a closed loop,
• forming a first insulating film around the first fin-shaped silicon layer and second fin-shaped silicon layer, and
• forming a first pillar-shaped silicon layer in an upper portion of the first fin-shaped silicon layer, and
• forming a second pillar-shaped silicon layer in an upper portion of the second fin-shaped silicon layer, the first pillar-shaped silicon layer having a width equal to a width of the first fin-shaped silicon layer and the second pillar-shaped silicon layer having a width equal to a width of the second fin-shaped silicon layer;
• after the first step, a second step comprising:
• forming diffusion layers by implanting an impurity into an upper portion of the first pillar-shaped silicon layer, an upper portion of the first fin-shaped silicon layer, and a lower portion of the first pillar-shaped silicon layer, and
• forming diffusion layers by implanting an impurity into an upper portion of the second pillar-shaped silicon layer, an upper portion of the second fin-shaped silicon layer, and a lower portion of the second pillar-shaped silicon layer;
• after the second step, a third step comprising:
• forming a gate insulating film on and around the first pillar-shaped silicon layer and second pillar-shaped silicon layer,
• forming a first polysilicon gate electrode and a second polysilicon gate electrode so as to cover the gate insulating film, and
• forming a polysilicon gate line, where an upper surface of a polysilicon after the first polysilicon gate electrode, the second polysilicon gate electrode, and the polysilicon gate line are formed is located at a higher position than the gate insulating film on the diffusion layer in the upper portion of the first pillar-shaped silicon layer and the gate insulating film on the diffusion layer in the upper portion of the second pillar-shaped silicon layer;
• after the third step, a fourth step comprising:
• forming a silicide in an upper portion of the diffusion layer formed in the upper portion of the first fin-shaped silicon layer and in an upper portion of the diffusion layer formed in the second fin-shaped silicon layer;
• after the fourth step, a fifth step comprising:
• depositing an interlayer insulating film, exposing the first polysilicon gate electrode, the second polysilicon gate electrode, and the polysilicon gate line,
• etching the first polysilicon gate electrode, the second polysilicon gate electrode, and the polysilicon gate line,
• then depositing a metal, and
• forming a first metal gate electrode, a second metal gate electrode, and a metal gate line, the metal gate line being connected to the first metal gate electrode and second metal gate electrode and extending in a direction perpendicular to a direction in which the first fin-shaped silicon layer and second fin-shaped silicon layer extend;
• and,
• after the fifth step, a sixth step comprising:
• forming a contact that is directly connected to the diffusion layer in the upper portion of the first pillar-shaped silicon layer and the diffusion layer in the upper portion of the second pillar-shaped silicon layer.