Method of Manufacturing a Reduced Free-Charge Carrier Lifetime Semiconductor Structure
AssigneeInfineon Technologies AG
InventorsHolger Ruething, Hans-Joachim Schulze, Frank Hille, Frank Pfirsch
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Abstract
A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure includes forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate, forming a body region between adjacent ones of the transistor gate structures and forming an end-of-range irradiation region between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.
Claims18
A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure, the method comprising:
- forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate;
- forming a body region between adjacent ones of the transistor gate structures;
- and
- forming an end-of-range irradiation region between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.
A method of manufacturing a power semiconductor device, the method comprising:
- providing a semiconductor substrate;
- forming a transistor gate structure in a trench arranged in the semiconductor substrate;
- forming a body region of a first conductivity type adjacent the transistor gate structure;
- forming a first highly-doped region of a second conductivity type in an upper portion of the body region;
- forming a drift zone of the second conductivity type below the body region;
- forming a second highly-doped region of the second conductivity type below the drift zone;
- and
- forming an end-of-range irradiation region adjacent the transistor gate structure, the end-of-range irradiation region having a plurality of vacancies.
Dependencies are inferred from the claim text.