Frequency Division
AssigneeST-Ericsson SA
InventorsNiko Mikkola, Petri Heliö, Paavo Väänänen
Life of this patent
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Abstract
A frequency divider comprises a signal generation stage arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronisation stage is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.
Claims25
1-24. (canceled)
A frequency divider comprising:
- a signal generation stage arranged to employ a clock signal at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal;
- and
- a synchronisation stage arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.
A frequency synthesiser comprising:
- a frequency divider comprising:
- a signal generation stage arranged to employ a clock signal at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal;
- and
- a synchronisation stage arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.
A wireless communication apparatus comprising:
- a frequency divider comprising:
- a signal generation stage arranged to employ a clock signal at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal;
- and
- a synchronisation stage arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.
A method of frequency division comprising:
- employing a clock signal at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal;
- and
- generating an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.
Dependencies are inferred from the claim text.