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US 2014/0210278 A1Published application
Capacitance Bank Systems and Methods
AssigneeIntel Deutschland GmbH
InventorsDavid Gaied, Ahmed Nader Mohieldin
Life of this patent
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Abstract
A capacitance bank system includes a plurality of voltage controlled capacitance cells and an output node. The plurality of capacitance cells have an anti-parallel configuration. The plurality of capacitance cells are configured to selectively provide cell capacitances. The output node is coupled to the plurality of capacitance cells. The output node is configured to provide an input capacitance step smaller than a minimum physical capacitor supported by a particular technology.
Claims21
A capacitance bank system comprising:
- a plurality of voltage controlled capacitance cells having an anti-parallel configuration and configured to selectively provide cell capacitances;
- and
- an output node coupled to the plurality of capacitance cells configured to provide an input capacitance.
A capacitance cell comprising:
- a first capacitor having a positive end coupled to a mid node and a negative end coupled to a control node, wherein the first capacitor has a first capacitance;
- a second capacitor having a positive end coupled to the control node and a negative end coupled to the mid node, wherein the second capacitor has a second capacitance;
- and
- wherein the first capacitance is provided at the mid node in a first state and the second capacitance is provided at the mid node in a second state.
1 more element
A method of using a capacitance cell, the method comprising:
- configuring a first capacitor and a second capacitor in an anti-parallel capacitance configuration;
- applying a control bit signal corresponding to a first state to a first end of the capacitance configuration;
- and
- providing a cell capacitance based on only the first capacitor at a second end of the capacitance configuration.
1 more element
Dependencies are inferred from the claim text.