Techniques for enhancing fracture resistance of interconnects

An integrated circuit comprising:

• a dielectric layer;
• a first circuit layer formed within the dielectric layer, the first circuit layer comprising a first plurality of filler lines including a first filler line;
• and
• a second circuit layer formed within the dielectric layer and adjacent to the first circuit layer, the second circuit layer comprising a second plurality of filler lines including a second filler line;
• wherein the second filler line includes a via extending therefrom and landing on the first filler line at a location at which the second filler line crosses over the first filler line.

An integrated circuit comprising:

• a first circuit layer comprising a first plurality of electrically isolated filler lines formed in a low-κ dielectric material having a dielectric constant that is less than the dielectric constant of silicon dioxide (SiO2);
• and
• a second circuit layer formed on the first circuit layer, the second circuit layer comprising a second plurality of electrically isolated filler lines formed in a low-κ dielectric material having a dielectric constant that is less than the dielectric constant of silicon dioxide (SiO2);
• wherein at least one filler line of the second plurality of filler lines is configured as a dual-damascene structure including a via extending therefrom and landing on a filler line of the first plurality of filler lines.