Nonvolatile memory bitcell

A nonvolatile memory device comprising an array of memory cells, wherein each of the memory cells includes:

• a select transistor comprising:
• a select transistor gate overlying a select transistor channel region;
• a select transistor source region adjacent to the select transistor channel region;
• and
• a select transistor drain region adjacent to the select transistor channel region, wherein the select transistor channel region is positioned between the select transistor source region and the select transistor channel region;
• and
• a bitcell transistor, comprising:
• a bitcell transistor gate overlying a bitcell transistor channel region of a bitcell transistor body;
• a bitcell transistor source region adjacent to the bitcell transistor channel region;
• and
• a bitcell transistor proximal drain region adjacent to the bitcell transistor channel region, wherein the bitcell transistor channel region is positioned between the bitcell transistor source region and the bitcell transistor proximal drain region;
• wherein an impurity concentration gradient of a junction between the bitcell source region and the bitcell transistor body is less than an impurity concentration gradient of a junction between the bitcell drain region and the bitcell transistor body.

A method of fabricating a nonvolatile memory, the method comprising:

• forming a memory cell, the memory cell comprising:
• a select transistor comprising symmetrically configured source-drain regions;
• and
• a bitcell transistor comprising asymmetrically configured source-drain regions and an Ohmically isolated transistor gate;
• wherein an impurity concentration gradient of a source-body junction of the bitcell transistor is less than an impurity concentration gradient of a drain-body junction of the bitcell transistor.