Integrated test circuit and method for manufacturing an integrated test circuit

A method for manufacturing an integrated test circuit comprising:

• providing a plurality of test structure elements, wherein each test structure element of the plurality of test structure elements comprises at least one supply line and at least one test line;
• providing a plurality of select transistors, wherein each select transistor of the plurality of select transistors is assigned to one corresponding test structure element, and wherein each select transistor comprises a first controlled region, a second controlled region, and a control region, wherein the second controlled region of each select transistor is respectively electrically connected to the supply line of the corresponding test structure element, so that each select transistor is unambiguous assigned to the corresponding test structure element;
• providing a plurality of contact pads, wherein each contact pad of a first set of contact pads of the plurality of contact pads is respectively electrically connected to the control region of corresponding select transistors, and wherein each contact pad of a second set of contact pads of the plurality of contact pads is respectively electrically connected to the first controlled region of corresponding select transistors, so that each select transistor is unambiguously assigned to respectively two contact pads of the plurality of contact pads and each test structure element of the plurality of test structure elements can be individually addressed by the plurality of contact pads.

An integrated test circuit, comprising:

• a plurality of test structure elements, wherein each test structure element of the plurality of test structure elements comprises at least one supply line and at least one test line;
• a plurality of pre-select transistors, wherein each pre-select transistor of the plurality of pre-select transistors comprises at least a first controlled region, a second controlled region, and a control region;
• a select structure comprising a plurality of select transistor arrangements, wherein each select transistor arrangement comprises a plurality of select transistors, wherein each select transistor arrangement of the plurality of select transistor arrangements is unambiguously assigned to one corresponding pre-select transistor, and wherein each select transistor of the select structure is clearly unambiguously assigned to one test structure element, wherein each select transistor of the select structure comprises a first controlled region, a second controlled region, and a control region;
• a plurality of electrical connections, wherein the second controlled region of each of the pre-select transistors is respectively electrically connected to the corresponding first controlled region of the plurality of select transistors of the corresponding select transistor arrangement, and wherein the second controlled region of each select transistor of the plurality of select transistors is respectively electrically connected to the supply line of the corresponding test structure element;
• a plurality of contact pads, wherein each contact pad of a first set of contact pads of the plurality of contact pads is respectively electrically connected to the control region of the corresponding pre-select transistors, wherein each contact pad of a second set of contact pads of the plurality of contact pads is respectively electrically connected to the first controlled region of the corresponding pre-select transistors, wherein each contact pad of a third set of contact pads of the plurality of contact pads is respectively electrically connected to the control region of the corresponding select transistors, so that each select transistor of the plurality of select transistors is unambiguously assigned to respectively three contact pads of the plurality of contact pads and each test structure element of the plurality of test structure elements can be individually addressed by the plurality of contact pads.

A method for manufacturing an integrated test circuit comprising:

• providing a plurality of test structure elements, wherein each test structure element of the plurality of test structure elements comprises at least one supply line and at least one test line;
• providing a plurality of pre-select transistors, wherein each pre-select transistor of the plurality of pre-select transistors comprises at least a first controlled region, a second controlled region, and a control region;
• providing a select structure comprising a plurality of select transistor arrangements, wherein each select transistor arrangement comprises a plurality of select transistors, wherein each select transistor arrangement of the plurality of select transistor arrangements is unambiguously assigned to one corresponding pre-select transistor, and wherein each select transistor of the select structure is clearly unambiguously assigned to one test structure element, wherein each select transistor of the select structure comprises a first controlled region, a second controlled region, and a control region;
• providing a plurality of electrical connections, wherein the second controlled region of each of the pre-select transistors is respectively electrically connected to the corresponding first controlled region of the plurality of select transistors of the corresponding select transistor arrangement, and wherein the second controlled region of each select transistor of the plurality of select transistors is respectively electrically connected to the supply line of the corresponding test structure element;
• providing a plurality of contact pads, wherein each contact pad of a first set of contact pads of the plurality of contact pads is respectively electrically connected to the control region of the corresponding pre-select transistors, wherein each contact pad of a second set of contact pads of the plurality of contact pads is respectively electrically connected to the first controlled region of the corresponding pre-select transistors, wherein each contact pad of a third set of contact pads of the plurality of contact pads is respectively electrically connected to the control region of the corresponding select transistors, so that each select transistor of the plurality of select transistors is unambiguously assigned to respectively three contact pads of the plurality of contact pads and each test structure element of the plurality of test structure elements can be individually addressed by the plurality of contact pads.