Self-aligned double patterning via enclosure design

A method for computing via enclosure rules, comprising:

• identifying, by at least one computing device, line termination modes in a self-aligned double patterning line pattern comprising a plurality of lines and vias;
• assigning, by the at least one computing device, a first via enclosure rule in response to identifying a set of aligned adjacent lines;
• and
• assigning, by the at least one computing device, a second via enclosure rule in response to identifying a set of misaligned adjacent lines.

A non-transitory computer-readable medium comprising instructions which, when executed by a processor, perform the steps of:

• identifying line termination modes in a self-aligned double patterning line pattern comprising a plurality of lines and vias;
• assigning a first via enclosure rule in response to identifying a line termination mode of inner vertex block mask, wherein the inner vertex block mask comprises at least one vertex that has an outer angle that is less than 180 degrees;
• and
• assigning a second via enclosure rule in response to identifying a line termination mode of outer vertex block mask, wherein the outer vertex block mask consists of vertices that have an outer angle that is greater than 180 degrees.