Method and system for designing 3d semiconductor package

A special purpose processor, comprising:

• a central processing unit;
• and
• a storage which stores a module for designing a three-dimensional (3D) net assignment between a plurality of first terminals included in a first semiconductor package, a plurality of second terminals included in a second semiconductor package disposed above or below the first semiconductor package, and connection terminals connecting the first semiconductor package and the second semiconductor package by an operation of the central processing unit,
• wherein the module comprises:
• receiving a first package layout parameter for the first terminals, a second package layout parameter for the second terminals, and a connection terminal layout parameter for the connection terminals to electrically connect terminals of the first semiconductor package to terminals of the second semiconductor package;
• generating an initial solution for a wiring between the first terminals, the second terminals and the connection terminals by applying a first sub-process to the first semiconductor package, second semiconductor package, and connection terminal layout parameters wherein said generating a first wiring connection layout by applying a first sub-process comprises generating an initial solution by applying a first sub-process to the first semiconductor package, second semiconductor package, and connection terminal layout parameters, and generating the first wiring connection layout by applying a second sub-process, which is different from the first sub-process, to the initial solution;
• and
• generating a first wiring connection layout by applying a second sub-process to the initial solution, wherein the second sub process includes determining a first reference vector at a center of the first wiring connection layout, sequentially numbering the second terminals and the connection terminals by rotating the first reference vector in a clockwise direction or counterclockwise direction, and connecting the second terminals and the connection terminals having the same number to each other;
• and
• designing the 3D net assignment from the first wiring connection layout by using a second process.

A three-dimensional semiconductor device, comprising:

• a first semiconductor package, including first package terminals;
• a second semiconductor package, including second package terminals;
• and
• a substrate, including connection terminals, wherein first package terminals are electrically connected to second package terminals through connection terminals, the connection layout between first package terminals, second package terminals, and connection terminals determined by first and second processes, wherein the first process establishes an initial layout using a plurality of connection terminals as reference points, then refines the layout by selecting initial layouts having preferable net lengths or byte skews, and wherein the second process establishes connections between connection terminals and second package terminals by sweeping connection and second package terminals, numbering the respective terminals in the order in which they are swept, and connecting like-numbered second package terminals to liked-numbered connection terminals.