Error protection for integrated circuits

A computer program product for configuring an array of storage cells, the computer program product comprising:

• a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising:
• computer readable program code configured to:
• determine a sensitive direction and an insensitive direction of the storage cells;
• add a first error control mechanism to the array of storage cells in the insensitive direction;
• and
• add a second error control mechanism to the array of storage cells in the sensitive direction;
• wherein the second error control mechanism has a higher Hamming distance than the first error control mechanism.

An integrated circuit comprising:

• an array of storage cells, wherein the storage cells comprise a sensitive direction and an insensitive direction;
• a first error control mechanism operable for detecting errors in the array of storage cells in the insensitive direction;
• and
• a second error control mechanism operable for detecting errors in the sensitive direction;
• wherein the second error control mechanism has a higher Hamming distance than the first error control mechanism.