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AssigneeMentor Graphics Corporation
InventorStephen Kenneth Sunter
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Various aspects of the present invention relate to techniques of measuring delays between edges of signals of a circuit. Alternating signals, synchronous to a first clock, are supplied to a plurality of nodes of the circuit. First samples of a plurality of signals associated with the alternating signals are captured using a first capture clock, of which sampling instants are synchronous to a second clock. Second samples of the first samples are then captured using a second capture clock, of which sampling instants are also synchronous to the second clock. The captured second samples are conveyed via a shift register to a plurality of modulo counters. The measured signal delay includes a timing skew associated with the first clock and a timing skew of the first capture clock but not a timing skew of the second capture clock.
A circuit for measuring a signal delay between an edge of a first alternating signal supplied to a first node of a circuit-under-test (CUT) and an edge of a second alternating signal supplied to a second node of the CUT, the first and second alternating signals being synchronous to a first clock, the circuit comprising:
A method for measuring delays between signal edges at nodes of a circuit, comprising:
Dependencies are inferred from the claim text.