US 2014/0208177 A1 · CIRCUITS AND METHODS FOR DYNAMIC ALLOCATION OF SCAN TEST RESOURCES

Abstract

A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.

Claims20

Dependent claims

A method of testing devices under test (DUTs), at least one DUT comprising N number of scan channels associated with M number of Input/Output (I/O) ports, the method comprising:

generating at least one control signal associated with a test pattern structure, the test pattern structure configured to be implemented to scan test the at least one DUT;
selecting M1 number of ports from among the M number of I/O ports so as to receive a scan input corresponding to the test pattern structure based on the at least one control signal;
selecting M2 number of ports from among the M number of I/O ports so as to provide a scan output corresponding to the test pattern structure based on the at least one control signal, each of M1 and M2 being a number selected from among a range of numbers between 0 and M, and a sum of M1 and M2 being less than or equal to M;
and
performing a scan testing of the at least one DUT based on a provision of the scan input to the M1 number of ports and a receipt of the scan output from the M2 number of ports.

2 more elements

A Device Under test (DUT) capable of being scan tested by a testing system, the DUT comprising:

M number of Input/Output (I/O) ports, each I/O port from among the M number of I/O ports configured to receive a scan input corresponding to a test pattern structure and provide a scan output corresponding to the test pattern structure;
a plurality of scan channels coupled with the M number of I/O ports and configured to receive the scan input and provide the scan output;
and
a selection circuit coupled with each I/O port from among the M number of I/O ports and each scan channel from among the plurality of scan channels, the selection circuit configured to:
select M1 number of I/O ports from among the M number of I/O ports to receive the scan input based on at least one control signal, and
select M2 number of I/O ports from among the M number of I/O ports to provide the scan output based on the at least one control signal, each of M1 and M2 being a number selected from among a range of numbers between 0 and M, and a sum of M1 and M2 being less than or equal to M.

3 more elements

A testing system for scan testing of Devices Under Tests (DUTs), at least one DUT comprising N number of scan channels associated with M number of Input/Output (I/O) ports, the testing system comprising:

a control circuit configured to generate at least one control signal based on a test pattern structure, the test pattern structure configured to be implemented to perform a scan testing of the at least one DUT, and the at least one control signal configured to enable:
a selection of M1 number of I/O ports from among the M number of I/O ports to receive a scan input corresponding to the test pattern structure based on the at least one control signal, and
a selection of M2 number of ports from among the M number of I/O ports to provide a scan output corresponding to the test pattern structure based on the at least one control signal, each of M1 and M2 being a number selected from among a range of numbers between 0 and M, and a sum of M1 and M2 being less than or equal to M, such that the scan testing is configured to be performed based on a provision of the scan input to the M1 number of ports and a receipt of the scan output from the M2 number of ports.

Dependencies are inferred from the claim text.

Circuits and methods for dynamic allocation of scan test resources

Life of this patent

Circuits and methods for dynamic allocation of scan test resources

Life of this patent

Abstract

Claims20