Memory access methods and apparatus

A memory module, comprising:

• a first memory (402f) having a first row (608);
• a second memory (402a) having a second row;
• and
• an address buffer (406) to latch a row address and a column address and forward the row and column addresses to the first and second memories, the first memory to selectively activate a first portion of the first row and the second memory to selectively activate a second portion of the second row in response to the row and column addresses, the first portion and the second portion activated without activating other portions of the first and second rows.

A memory, comprising:

• a data interface (816, 902, 1004);
• and
• an integrated circuit memory die (806g) in communication with the data interface, the integrated circuit memory die comprising:
• a plurality of banks (808);
• a plurality of subarrays (810a, 810b) in each bank;
• and
• bitlines (812) in each bank, first ones of the bitlines corresponding to a first one of the banks being addressable to access an entire cache line in a single one of the subarrays of the first bank.

A memory module, comprising:

• a first memory (806g) having a first subarray (810a);
• a second memory (806a) having a second subarray;
• first bitlines (812) in the first memory to enable access to an entire first cache line in the first subarray;
• and
• second bitlines in the second memory to enable access to an entire second cache line in the second subarray.