Apparatus and method for dynamically aligned source synchronous receiver

An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising:

• a microprocessor, comprising:
• a synchronous lag receiver, configured to receive one of a plurality of radially distributed strobes and a data bit, and configured to delay registering of said data bit by a propagation time, said synchronous lag receiver comprising:
• a first plurality of matched inverters, configured to generate successively delayed versions of said data bit;
• a first mux, coupled to said first plurality of matched inverters, configured to receive a value on a lag bus that indicates said propagation time, and configured to select one of said successively delayed versions of said data bit that corresponds to said value;
• and
• a bit receiver, configured to receive said one of said successively delayed versions of said data bit and one of a plurality of radially distributed strobe signals, and configured to register the state of said one of said successively delayed versions of said data bit upon assertion of said one of a plurality of radially distributed strobe signals.

A method that compensates for misalignment on a synchronous data bus, the method comprising:

• first receiving one of a plurality of radially distributed strobes and a data bit, and delaying registering of the data bit by a propagation time, said first receiving comprising:
• first generating successively delayed versions of the data bit;
• second receiving a value on a lag bus that indicates the propagation time, and first selecting one of the successively delayed versions of the data bit that corresponds to said value;
• and
• registering the state of the one of said successively delayed versions of the data bit upon assertion of one of a plurality of radially distributed strobe signals.