Automatic source synchronous bus signal alignment compensation mechanism
AssigneeVIA Technologies, Inc.
InventorsVanessa S. Canac, James R. Lundberg
Life of this patent
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AssigneeVIA Technologies, Inc.
InventorsVanessa S. Canac, James R. Lundberg
Estimating the term…
An apparatus including a Joint Test Action Group (JTAG) interface and a bit lag control element. The JTAG interface receives information that indicates an amount to adjust a propagation time. The bit lag control element measures the propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and generates a value indicating an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value indicating the propagation time. The adjust logic adjusts the second value by the amount prescribed by the JTAG interface to yield a third value. The gray encoder gray encodes the third value to generate the value on the lag bus.
An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising:
An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising:
A method that compensates for misalignment on a synchronous data bus, the method comprising:
Dependencies are inferred from the claim text.