US 2014/0208142 A1 · SEMICONDUCTOR DEVICE

Abstract

Supply of power to a plurality of circuits is controlled efficiently depending on usage conditions and the like of the circuits. An address monitoring circuit monitors whether a cache memory and an input/output interface are in an access state or not, and performs power gating in accordance with the state of the cache memory and the input/output interface. The address monitoring circuit acquires and monitors an address signal between a signal processing circuit and the cache memory or the input/output interface periodically. When one of the cache memory and the input/output interface is in a standby state and the other is in the access state, power gating is performed on the circuit that is in the standby state.

Claims20

Dependent claims

A semiconductor device comprising:

a signal processing circuit, a cache memory, and an input/output interface electrically connected to a bus line;
an address monitoring circuit monitoring whether the signal processing circuit, the cache memory, and the input/output interface are in an access state or not;
first to third switches electrically connected to the signal processing circuit, the cache memory, and the input/output interface, respectively, and configured to select whether to supply power to the signal processing circuit, the cache memory, and the input/output interface in response to a power gating control signal;
and
a power control circuit outputting the power gating control signal in accordance with a state of the signal processing circuit, a state of the cache memory, and a state of the input/output interface which are monitored by the address monitoring circuit.

2 more elements

A semiconductor device comprising:

a bus line;
a signal processing circuit;
a cache memory configured to be supplied with a first address signal from the signal processing circuit through the bus line;
an input/output interface configured to be supplied with a second address signal from the signal processing circuit through the bus line;
an address monitoring circuit acquiring the first address signal and the second address signal;
and
a power control circuit performing power gating on the cache memory and the input/output interface,
wherein the power control circuit is configured to select whether power gating of the cache memory is performed or not in response to the first address signal, and
wherein the power control circuit is configured to select whether power gating of the input/output interface is performed or not in response to the second address signal.

6 more elements

A semiconductor device comprising:

a bus line;
a signal processing circuit;
a cache memory configured to be supplied with a first address signal from the signal processing circuit through the bus line;
an input/output interface configured to be supplied with a second address signal from the signal processing circuit through the bus line;
a sub-signal processing circuit configured to be booted up by the signal processing circuit;
an address monitoring circuit acquiring the first address signal and the second address signal;
and
a power control circuit performing power gating on the signal processing circuit, the cache memory, and the input/output interface,
wherein the power control circuit is configured to select whether power gating of the signal processing circuit is performed or not according to whether the sub-signal processing circuit is booted up or not,
wherein the power control circuit is configured to select whether power gating of the cache memory is performed or not in response to the first address signal, and
wherein the power control circuit is configured to select whether power gating of the input/output interface is performed or not in response to the second address signal.

8 more elements

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims20