Dynamically controlling interconnect frequency in a processor

A system comprising:

• a processor including a plurality of cores, a plurality of voltage regulators each to independently provide a voltage to at least one of the plurality of cores, and system agent circuitry including at least one cache memory, a memory controller and an interconnect to couple the plurality of cores and the at least one cache memory, the interconnect including a plurality of interface units each to couple the interconnect to one of the plurality of cores, wherein each of the interface units includes a traffic sensor to measure traffic at a location of the interconnect associated with the interface unit, the system agent circuitry further including a power controller to receive information regarding the traffic from at least some of the plurality of traffic sensors to control a frequency of the interconnect based on at least some of the information.

(canceled)

(canceled)

(canceled)

(canceled)