Systems and method for unblocking a pipeline with spontaneous load deferral and conversion to prefetch

A machine-accessible medium including data that, when accessed by a machine, cause the machine to perform operations comprising:

• determining whether a speculative load instruction encounters a long latency condition;
• spontaneously deferring the speculative load instruction if the speculative load instruction encounters the long latency condition;
• initiating a prefetch of a translation or of data requiring long latency access if the speculative load instruction encounters the long latency condition;
• and
• determining whether the speculative load instruction is needed.

A processor architecture, comprising:

• a register file;
• a first translation lookaside buffer (TLB) coupled to the register file, the first TLB with a number of ports for mapping virtual addresses to physical addresses;
• a second TLB coupled to the first TLB, the second TLB to perform a hardware page walk that is initiated when the load speculative instruction misses the first TLB;
• cache storage to store data including a physical address associated with the load speculative instruction;
• and
• processing logic that is configured to determine whether a speculative load instruction encounters a long latency TLB miss of the first TLB, to spontaneously defer the speculative load instruction by setting a bit in the register file if the speculative load instruction encounters the long latency TLB miss, and to initiate a hardware page walk to the second TLB if the speculative load instruction encounters the long latency TLB miss.

A system, comprising:

• one or more processors comprising,
• a translation lookaside buffer (TLB), the first TLB with a number of ports for mapping virtual addresses to physical addresses;
• a first cache storage coupled to the TLB, the first cache storage to receive a physical address associated with a speculative load instruction when the speculative load instruction hits the TLB;
• a second cache storage coupled to the first cache storage, the second cache storage to store data including data associated with a physical address that is associated with the speculative load instruction;
• wherein the one or more processors are configured to execute instructions to determine whether the physical address associated with the speculative load instruction is located in the first cache storage, to spontaneously defer the speculative load instruction by setting a bit in a register file when the physical address is not located in the first cache storage, and to determine whether the physical address associated with the speculative load instruction is located in the second cache storage.