US 2014/0208074 A1 · INSTRUCTION SCHEDULING FOR A MULTI-STRAND OUT-OF-ORDER PROCESSOR

Abstract

In one embodiment, a multi-strand system with a pipeline includes a front-end unit, an instruction scheduling unit (ISU), and a back-end unit. The front-end unit performs an out-of-order fetch of interdependent instructions queued using a front-end buffer. The ISU dedicates two hardware entries per strand for checking operand-readiness of an instruction and for determining an execution port to which the instruction is dispatched. The back-end unit receives instructions dispatched from the hardware device and stores the instructions until they are executed. Other embodiments are described and claimed.

Claims30

Dependent claims

A method, comprising:

fetching a strand of interdependent instructions for execution, wherein the strand of interdependent instructions are fetched out of order;
dedicating a first hardware resource and a second hardware resource for the strand;
storing an instruction of the strand using the first hardware resource;
determining whether the instruction stored using the first hardware resource is operand-ready;
storing the instruction using the second hardware resource when the instruction is operand-ready;
and
determining an available execution port for the instruction stored using the second hardware resource.

4 more elements

Dependencies are inferred from the claim text.

Instruction scheduling for a multi-strand out-of-order processor

Life of this patent

Instruction scheduling for a multi-strand out-of-order processor

Life of this patent

Abstract

Claims30