Systems and methods for interfacing master and slave processors

A method comprising:

• transmitting data from a first processor through an isolation barrier;
• determining if the data includes a custom pattern;
• if the data does not includes the custom pattern, using a serial peripheral interface (SPI) communications protocol;
• if the data includes the custom pattern, using a custom communications protocol;
• transmitting the data to a second processor;
• building a reply by using a reply register;
• communicating the reply to the first processor through the isolation barrier.

A system comprising:

• a serial peripheral interface (SPI) bridge configured to communicatively couple a first processor having a SPI port to a second processor comprising:
• a data multiplexor configured to route signals for the first processor;
• a first register configured to communicatively couple the data multiplexor to the first processor;
• an output pin control communicatively coupled to the data multiplexor and configured to control a device;
• a serial digital interface (SDI) combinatorial logic system;
• a second register communicatively coupled to a second processor through the SDI combinatorial logic system;
• a reply register communicatively coupled to the data multiplexor, wherein the first processor is configured to use the data multiplexor to reply to a command issued by the second processor through an isolation barrier.